Samsung starts preparing for production of first 3nm Exynos chip, possibly for Galaxy S25

Taping out is the final stage of a semiconductor chip design phase. In this process, the final design file is sent to the foundry so they can create masks used for mass production.

The First Samsung Exynos chip using the 3nm process is now almost ready for production

Samsung's first high-performance mobile chip features a CPU, a GPU, and several IP blocks from Synopsis. While the company has been making 3nm chips since the end of 2022, those chips were fairly simple and used for cryptocurrency mining. This is the first time Samsung Foundry seems ready to produce an advanced high-performance mobile chip. This chip is likely for the Galaxy Watch 7 (most likely) or the Galaxy S25 series.

The South Korean firm reportedly used the Synopsys.ai EDA software to fine-tune the chip's design, improve its performance, and maximize yields. Samsung's engineers also used the Synopsys Fusion Compiler to achieve higher performance, lower power consumption, and optimize the chip area (PPA). If these claims are true, we could see a noticeable improvement in Samsung's next high-end mobile chip. However, we still don't know whether this chip uses Samsung Foundry's first-generation 3nm (SF3E) or second-generation 3nm process (SF3) process. It would most likely be the latter, as it is more suitable for more complex chips like smartphone SoCs.

Kijoon Hong, VP of Samsung's System LSI arm, said, “Our longstanding collaboration has delivered leading-edge SoC designs. This is a remarkable milestone for successfully achieving the highest performance, power, and area on the most advanced mobile CPU cores and SoC designs in collaboration with Synopsys. Not only have we demonstrated that AI-driven solutions can help us achieve PPA targets for even the most advanced GAA process technologies, but through our partnership, we have established an ultra-high-productivity design system that is consistently delivering impressive results.”

Samsung used Synopsis' chip design automation tools for faster performance and lower power consumption

Samsung and Synopsis claim the latter's design automation tools helped improve the chip's clock speed by 300MHz while cutting down power consumption by 10%. Engineers used design partitioning optimization, Multi-Source Clock Tree Synthesis (MSCTS), smart wire optimization, and a simpler hierarchical approach. Synopsys Fusion Compiler helped them do all these tasks much faster, skipping weeks of manual design work.

In the past, chips made by Samsung Foundry had issues related to higher power consumption and performance throttling under sustained loads. The company's GAA design was expected to solve those issues, but no other chip firm used it to make smartphone processors or other high-performance chips. The first 3nm Exynos chip will reveal whether those issues have been solved.