Samsung starts production of 3nm semiconductor chips with GAA architecture

With MBCFET (Multi-Bridge-Channel FET) GAA architecture, Samsung's 3nm chips get higher power efficiency by reducing supply voltage and enhancing the drive current capability. Samsung is also using nanosheet transistors in semiconductor chips for high-performance smartphone processors.

Compared to nanowire technology, nanosheets with wider channels allow higher performance and better efficiency. By adjusting the nanosheet width, Samsung's clients can customize power usage and performance according to their needs.

Compared to 5nm chips, the South Korean foundry firm is quoting a 23% improved performance, a 45% reduction in power usage, and an area reduction of 16%. The company's second-generation 3nm chips will offer 50% better power efficiency, 30% better performance, and 35% less area.

To help its chip clients and partners design better chips and verify their designs, Samsung Foundry is providing a stable design environment. Clients can reduce the time required for designing chips, verification and sign-off process, and boosting product reliability through SAFE (Samsung Advanced Foundry Ecosystem) partners, including Ansys, Cadence, Siemens, and Synopsys.

Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics, said, “Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry's first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world's first 3nm process with the MBCFETTM. We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology.”

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