Samsung develops key technology for making truly next-gen chips

Samsung is one of the world’s largest semiconductor chip makers, and it claims to have developed a new technology that could help enable truly next-generation chips. The South Korean firm’s new 3D Stacked FET architecture changes how transistors are arranged, potentially making it possible to create smaller, denser, and significantly more powerful chips.

Samsung Electronics recently presented a paper titled “First Demonstration of 3D Stacked FETs at Gate Pitch of 42nm Featuring Triple-Stacked Nanosheet Channels for Advanced Logic Applications” at the 2026 VLSI Symposium. At the conference, which was held from June 14 to June 16, 2026, Samsung’s paper was selected as the Best Paper among more than 1,000 submissions and received a score of 8.29 out of 10. It was also chosen as one of the 2026 VLSI Technical Highlights and featured in the conference’s official press kit.

The VLSI Symposium is one of the semiconductor industry’s most important technical conferences, where researchers, scientists, and engineers discuss emerging Very Large Scale Integration (VLSI) technologies and breakthrough innovations.

Traditionally, semiconductor technology has advanced by shrinking transistors to fit more of them into the same area, improving both performance and power efficiency. However, there are physical limits to how small individual transistors can become. Despite decades of innovation, transistors have largely remained arranged side by side on a two-dimensional plane.

Over the years, transistor architectures have evolved from planar transistors to FinFETs and, more recently, Gate-All-Around (GAA) transistors. Samsung has now developed a technology that vertically stacks two different types of transistors, n-type and p-type, on top of each other. This approach can significantly reduce the amount of space required on a chip.

While the concept may sound straightforward, vertically stacking transistors introduces several challenges, including power delivery, manufacturing uniformity, and electrical interference. Samsung says it addressed these issues by:

Samsung then demonstrated the technology using a 42nm gate pitch, which refers to the distance between adjacent transistor gates. This achievement suggests that the company’s 3D Stacked FET architecture could be applied to advanced process nodes in the future. Samsung also evaluated the technology’s uniformity by comparing the electrical characteristics of multiple structures across a wafer and found the results to be consistent.

This new technology represents a significant shift away from traditional planar chip designs toward a true three-dimensional transistor architecture. Such an approach could enable chips with much higher transistor density, better performance, and improved power efficiency. Samsung has not revealed when the technology could be commercialized or used in mass-produced products.