Samsung is using a co-design approach to optimize its next-gen 2nm chips

Samsung recently showcased its next-generation 2nm semiconductor fabrication process at its SAFE Forum 2026 event in South Korea. The company also explained how it is working with several partners to optimize chip manufacturing technology from the earliest stages of chip design.

During the SAFE Forum 2026 event held at Samsung Electronics’ Seocho headquarters earlier today, Samsung Foundry unveiled its next-generation 2nm process technology. The company is using a methodology called Design Technology Co-Optimization (DTCO), which allows engineers to optimize both the chip’s design and manufacturing process together instead of treating them as separate steps.

As part of this effort, Samsung is working with more than 21 partner companies that specialize in Electronic Design Automation (EDA) software, Intellectual Property (IP) blocks, and other chip design technologies.

The DTCO approach helps Samsung strike a better balance between chip size, manufacturing cost, power efficiency, performance, and production yield, which is the percentage of chips that work correctly after manufacturing. The company also said it is focusing on improving SRAM, a type of ultra-fast memory built directly into processors that is critical for AI workloads because it stores data that the processor needs to access immediately.

More than 400 representatives from Samsung’s 21 partner companies attended the event, where they showcased technologies and tools that help customers design chips for Samsung Foundry’s manufacturing processes.

South Korean AI accelerator startup Rebellion presented a case study demonstrating how Samsung’s ecosystem approach helped it develop the Rebel100 NPU using Samsung Foundry’s 4nm process. This chip offers 1,024 TFLOPs of performance with 600W power consumption and uses Samsung's HBM3E memory. Samsung believes collaborations like this will make it easier for customers to adopt its upcoming 2nm process technology.

Samsung also highlighted how it is strengthening partnerships with global artificial intelligence (AI) and high-performance computing (HPC) companies, as well as South Korea’s semiconductor industry, with the goal of becoming a key hub for the AI semiconductor ecosystem.

The company is also working with South Korea’s Ministry of Trade, Industry and Energy on initiatives such as the M.AX Alliance and the K-CHIPS project to develop more AI semiconductor talent and support local fabless chip companies through its Multi-Project Wafer (MPW) program.

An MPW program allows multiple companies to test prototype chip designs on a shared production wafer, dramatically reducing development costs before committing to mass production.